RT-Thread_v4.1.1
This commit is contained in:
552
libcpu/arm/cortex-r4/start_ccs.asm
Normal file
552
libcpu/arm/cortex-r4/start_ccs.asm
Normal file
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;-------------------------------------------------------------------------------
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; sys_core.asm
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;
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; (c) Texas Instruments 2009-2013, All rights reserved.
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;
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.text
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.arm
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.ref _c_int00
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.def _reset
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.asmfunc
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_reset
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;-------------------------------------------------------------------------------
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; Initialize CPU Registers
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; After reset, the CPU is in the Supervisor mode (M = 10011)
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mov r0, lr
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mov r1, #0x0000
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mov r2, #0x0000
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mov r3, #0x0000
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mov r4, #0x0000
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mov r5, #0x0000
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mov r6, #0x0000
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mov r7, #0x0000
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mov r8, #0x0000
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mov r9, #0x0000
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mov r10, #0x0000
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mov r11, #0x0000
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mov r12, #0x0000
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mov r13, #0x0000
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mrs r1, cpsr
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msr spsr_cxsf, r1
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; Switch to FIQ mode (M = 10001)
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cps #17
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mov lr, r0
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mov r8, #0x0000
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mov r9, #0x0000
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mov r10, #0x0000
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mov r11, #0x0000
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mov r12, #0x0000
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mrs r1, cpsr
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msr spsr_cxsf, r1
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; Switch to IRQ mode (M = 10010)
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cps #18
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch to Abort mode (M = 10111)
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cps #23
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch to Undefined Instruction Mode (M = 11011)
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cps #27
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
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cps #31
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mov lr, r0
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mrs r1,cpsr
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msr spsr_cxsf, r1
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; Switch back to Supervisor Mode (M = 10011)
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cps #19
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; Turn on FPV coprocessor
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mrc p15, #0x00, r2, c1, c0, #0x02
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orr r2, r2, #0xF00000
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mcr p15, #0x00, r2, c1, c0, #0x02
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.if (RT_VFP_LAZY_STACKING) = 0
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fmrx r2, fpexc
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orr r2, r2, #0x40000000
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fmxr fpexc, r2
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fmdrr d0, r1, r1
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fmdrr d1, r1, r1
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fmdrr d2, r1, r1
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fmdrr d3, r1, r1
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fmdrr d4, r1, r1
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fmdrr d5, r1, r1
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fmdrr d6, r1, r1
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fmdrr d7, r1, r1
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fmdrr d8, r1, r1
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fmdrr d9, r1, r1
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fmdrr d10, r1, r1
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fmdrr d11, r1, r1
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fmdrr d12, r1, r1
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fmdrr d13, r1, r1
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fmdrr d14, r1, r1
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fmdrr d15, r1, r1
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.endif
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;-------------------------------------------------------------------------------
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; Initialize Stack Pointers
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cps #17
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ldr sp, fiqSp
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cps #18
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ldr sp, irqSp
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cps #23
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ldr sp, abortSp
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cps #27
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ldr sp, undefSp
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cps #31
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ldr sp, userSp
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cps #19
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ldr sp, svcSp
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bl next1
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next1
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bl next2
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next2
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bl next3
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next3
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bl next4
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next4
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ldr lr, int00ad
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bx lr
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int00ad .word _c_int00
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userSp .word 0x08000000+0x00001000
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svcSp .word 0x08000000+0x00001000+0x00000100
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fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
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irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
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abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
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undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Enable RAM ECC Support
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.def _coreEnableRamEcc_
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.asmfunc
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_coreEnableRamEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Disable RAM ECC Support
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.def _coreDisableRamEcc_
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.asmfunc
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_coreDisableRamEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Enable Flash ECC Support
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.def _coreEnableFlashEcc_
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.asmfunc
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_coreEnableFlashEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x02000000
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dmb
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Disable Flash ECC Support
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.def _coreDisableFlashEcc_
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.asmfunc
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_coreDisableFlashEcc_
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x02000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get data fault status register
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.def _coreGetDataFault_
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.asmfunc
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_coreGetDataFault_
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mrc p15, #0, r0, c5, c0, #0
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear data fault status register
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.def _coreClearDataFault_
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.asmfunc
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_coreClearDataFault_
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c0, #0
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get instruction fault status register
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.def _coreGetInstructionFault_
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.asmfunc
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_coreGetInstructionFault_
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mrc p15, #0, r0, c5, c0, #1
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear instruction fault status register
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.def _coreClearInstructionFault_
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.asmfunc
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_coreClearInstructionFault_
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c0, #1
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get data fault address register
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.def _coreGetDataFaultAddress_
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.asmfunc
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_coreGetDataFaultAddress_
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mrc p15, #0, r0, c6, c0, #0
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear data fault address register
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.def _coreClearDataFaultAddress_
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.asmfunc
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_coreClearDataFaultAddress_
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c6, c0, #0
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get instruction fault address register
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.def _coreGetInstructionFaultAddress_
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.asmfunc
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_coreGetInstructionFaultAddress_
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mrc p15, #0, r0, c6, c0, #2
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear instruction fault address register
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.def _coreClearInstructionFaultAddress_
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.asmfunc
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_coreClearInstructionFaultAddress_
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c6, c0, #2
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get auxiliary data fault status register
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.def _coreGetAuxiliaryDataFault_
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.asmfunc
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_coreGetAuxiliaryDataFault_
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mrc p15, #0, r0, c5, c1, #0
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear auxiliary data fault status register
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.def _coreClearAuxiliaryDataFault_
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.asmfunc
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_coreClearAuxiliaryDataFault_
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c1, #0
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Get auxiliary instruction fault status register
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.def _coreGetAuxiliaryInstructionFault_
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.asmfunc
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_coreGetAuxiliaryInstructionFault_
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mrc p15, #0, r0, c5, c1, #1
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear auxiliary instruction fault status register
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.def _coreClearAuxiliaryInstructionFault_
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.asmfunc
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_coreClearAuxiliaryInstructionFault_
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stmfd sp!, {r0}
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mov r0, #0
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mrc p15, #0, r0, c5, c1, #1
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ldmfd sp!, {r0}
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bx lr
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Clear ESM CCM errorss
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.def _esmCcmErrorsClear_
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.asmfunc
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_esmCcmErrorsClear_
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stmfd sp!, {r0-r2}
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ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
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ldr r2, ESMSR1_ERR_CLR
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str r2, [r0] ; clear the ESMSR1 register
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ldr r0, ESMSR2_REG ; load the ESMSR2 status register address
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ldr r2, ESMSR2_ERR_CLR
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str r2, [r0] ; clear the ESMSR2 register
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ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address
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ldr r2, ESMSSR2_ERR_CLR
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str r2, [r0] ; clear the ESMSSR2 register
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ldr r0, ESMKEY_REG ; load the ESMKEY register address
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mov r2, #0x5 ; load R2 with 0x5
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str r2, [r0] ; clear the ESMKEY register
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ldr r0, VIM_INTREQ ; load the INTREQ register address
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ldr r2, VIM_INT_CLR
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str r2, [r0] ; clear the INTREQ register
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ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
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ldr r2, CCMR4_ERR_CLR
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str r2, [r0] ; clear the CCMR4 status register
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ldmfd sp!, {r0-r2}
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bx lr
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ESMSR1_REG .word 0xFFFFF518
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ESMSR2_REG .word 0xFFFFF51C
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ESMSR3_REG .word 0xFFFFF520
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ESMKEY_REG .word 0xFFFFF538
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ESMSSR2_REG .word 0xFFFFF53C
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CCMR4_STAT_REG .word 0xFFFFF600
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ERR_CLR_WRD .word 0xFFFFFFFF
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CCMR4_ERR_CLR .word 0x00010000
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ESMSR1_ERR_CLR .word 0x80000000
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ESMSR2_ERR_CLR .word 0x00000004
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ESMSSR2_ERR_CLR .word 0x00000004
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VIM_INT_CLR .word 0x00000001
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VIM_INTREQ .word 0xFFFFFE20
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.endasmfunc
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;-------------------------------------------------------------------------------
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; Work Around for Errata CORTEX-R4#57:
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;
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; Errata Description:
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; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
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; Workaround:
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; Disable out-of-order single-precision floating point
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; multiply-accumulate instruction completion
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.def _errata_CORTEXR4_57_
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.asmfunc
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_errata_CORTEXR4_57_
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push {r0}
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mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
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orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
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mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
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||||
pop {r0}
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||||
bx lr
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||||
.endasmfunc
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||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; Work Around for Errata CORTEX-R4#66:
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||||
;
|
||||
; Errata Description:
|
||||
; Register Corruption During A Load-Multiple Instruction At
|
||||
; an Exception Vector
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||||
; Workaround:
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; Disable out-of-order completion for divide instructions in
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; Auxiliary Control register
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||||
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||||
.def _errata_CORTEXR4_66_
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||||
.asmfunc
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||||
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||||
_errata_CORTEXR4_66_
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push {r0}
|
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mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
|
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orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
|
||||
; for divide instructions.)
|
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mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
|
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pop {r0}
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bx lr
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.endasmfunc
|
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.def turnon_VFP
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||||
.asmfunc
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turnon_VFP
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; Enable FPV
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STMDB sp!, {r0}
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fmrx r0, fpexc
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orr r0, r0, #0x40000000
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fmxr fpexc, r0
|
||||
LDMIA sp!, {r0}
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subs pc, lr, #4
|
||||
.endasmfunc
|
||||
|
||||
_push_svc_reg .macro
|
||||
sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */
|
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stmia sp, {r0 - r12} ;/* Calling r0-r12 */
|
||||
mov r0, sp
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||||
mrs r6, spsr ;/* Save CPSR */
|
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str lr, [r0, #15*4] ;/* Push PC */
|
||||
str r6, [r0, #16*4] ;/* Push CPSR */
|
||||
cps #0x13
|
||||
str sp, [r0, #13*4] ;/* Save calling SP */
|
||||
str lr, [r0, #14*4] ;/* Save calling PC */
|
||||
.endm
|
||||
|
||||
.ref rt_hw_trap_svc
|
||||
.def vector_svc
|
||||
.asmfunc
|
||||
vector_svc:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_svc
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
.ref rt_hw_trap_pabt
|
||||
.def vector_pabort
|
||||
.asmfunc
|
||||
vector_pabort:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_pabt
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
.ref rt_hw_trap_dabt
|
||||
.def vector_dabort
|
||||
.asmfunc
|
||||
vector_dabort:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_dabt
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
.ref rt_hw_trap_resv
|
||||
.def vector_resv
|
||||
.asmfunc
|
||||
vector_resv:
|
||||
_push_svc_reg
|
||||
bl rt_hw_trap_resv
|
||||
sub pc, pc, #-4
|
||||
.endasmfunc
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; C++ construct table pointers
|
||||
|
||||
.def __TI_PINIT_Base, __TI_PINIT_Limit
|
||||
.weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
|
||||
|
||||
__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
|
||||
__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
Reference in New Issue
Block a user