RT-Thread_v4.1.1
This commit is contained in:
449
libcpu/arm/zynqmp-r5/cache.c
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449
libcpu/arm/zynqmp-r5/cache.c
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/*
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* Copyright (c) 2006 - 2021, RT-Thread Development Team
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* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
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* Copyright (c) 2021 WangHuachen. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Change Logs:
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* Date Author Notes
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* 2020-03-19 WangHuachen first version
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* 2021-05-10 WangHuachen add more functions
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*/
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#include <stdint.h>
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#include <rthw.h>
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#include <rtdef.h>
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#include "xpseudo_asm_gcc.h"
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#include "xreg_cortexr5.h"
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#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */
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typedef intptr_t INTPTR;
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typedef rt_uint32_t u32;
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#if defined (__GNUC__)
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#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
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XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
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#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
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XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
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#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
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XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
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#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
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XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
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#elif defined (__ICCARM__)
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#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
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XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
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#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \
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XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
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#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
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XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
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#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \
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XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
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#endif
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void Xil_DCacheEnable(void);
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void Xil_DCacheDisable(void);
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void Xil_DCacheInvalidate(void);
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void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
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void Xil_DCacheFlush(void);
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void Xil_DCacheFlushRange(INTPTR adr, u32 len);
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void Xil_DCacheInvalidateLine(INTPTR adr);
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void Xil_DCacheFlushLine(INTPTR adr);
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void Xil_DCacheStoreLine(INTPTR adr);
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void Xil_ICacheEnable(void);
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void Xil_ICacheDisable(void);
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void Xil_ICacheInvalidate(void);
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void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
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void Xil_ICacheInvalidateLine(INTPTR adr);
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void Xil_DCacheEnable(void)
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{
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register u32 CtrlReg;
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/* enable caches only if they are disabled */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) == 0x00000000U)
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{
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/* invalidate the Data cache */
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Xil_DCacheInvalidate();
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/* enable the Data cache */
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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}
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void Xil_DCacheDisable(void)
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{
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register u32 CtrlReg;
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/* clean and invalidate the Data cache */
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Xil_DCacheFlush();
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/* disable the Data cache */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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void Xil_DCacheInvalidate(void)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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/*invalidate all D cache*/
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mtcp(XREG_CP15_INVAL_DC_ALL, 0);
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mtcpsr(currmask);
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}
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void Xil_DCacheInvalidateLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
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{
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const u32 cacheline = 32U;
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u32 end;
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u32 tempadr = adr;
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u32 tempend;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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if (len != 0U)
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{
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end = tempadr + len;
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tempend = end;
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/* Select L1 Data cache in CSSR */
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
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if ((tempadr & (cacheline - 1U)) != 0U)
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{
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tempadr &= (~(cacheline - 1U));
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Xil_DCacheFlushLine(tempadr);
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}
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if ((tempend & (cacheline - 1U)) != 0U)
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{
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tempend &= (~(cacheline - 1U));
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Xil_DCacheFlushLine(tempend);
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}
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while (tempadr < tempend)
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{
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/* Invalidate Data cache line */
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asm_inval_dc_line_mva_poc(tempadr);
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tempadr += cacheline;
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}
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}
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dsb();
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mtcpsr(currmask);
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}
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void Xil_DCacheFlush(void)
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{
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register u32 CsidReg, C7Reg;
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u32 CacheSize, LineSize, NumWays;
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u32 Way, WayIndex, Set, SetIndex, NumSet;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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/* Select cache level 0 and D cache in CSSR */
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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#if defined (__GNUC__)
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CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
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#endif
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/* Determine Cache Size */
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CacheSize = (CsidReg >> 13U) & 0x000001FFU;
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CacheSize += 0x00000001U;
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CacheSize *= (u32)128; /* to get number of bytes */
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/* Number of Ways */
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NumWays = (CsidReg & 0x000003ffU) >> 3U;
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NumWays += 0x00000001U;
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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NumSet = CacheSize / NumWays;
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NumSet /= (0x00000001U << LineSize);
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Way = 0U;
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Set = 0U;
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/* Invalidate all the cachelines */
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for (WayIndex = 0U; WayIndex < NumWays; WayIndex++)
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{
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for (SetIndex = 0U; SetIndex < NumSet; SetIndex++)
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{
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C7Reg = Way | Set;
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/* Flush by Set/Way */
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asm_clean_inval_dc_line_sw(C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set = 0U;
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Way += 0x40000000U;
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}
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/* Wait for flush to complete */
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dsb();
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mtcpsr(currmask);
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mtcpsr(currmask);
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}
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void Xil_DCacheFlushLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
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/* Wait for flush to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_DCacheFlushRange(INTPTR adr, u32 len)
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{
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u32 LocalAddr = adr;
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const u32 cacheline = 32U;
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u32 end;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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if (len != 0x00000000U)
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{
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/* Back the starting address up to the start of a cache line
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* perform cache operations until adr+len
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*/
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end = LocalAddr + len;
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LocalAddr &= ~(cacheline - 1U);
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while (LocalAddr < end)
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{
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/* Flush Data cache line */
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asm_clean_inval_dc_line_mva_poc(LocalAddr);
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LocalAddr += cacheline;
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}
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}
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dsb();
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mtcpsr(currmask);
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}
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void Xil_DCacheStoreLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
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/* Wait for store to complete */
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dsb();
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isb();
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mtcpsr(currmask);
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}
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void Xil_ICacheEnable(void)
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{
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register u32 CtrlReg;
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/* enable caches only if they are disabled */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) == 0x00000000U)
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{
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/* invalidate the instruction cache */
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mtcp(XREG_CP15_INVAL_IC_POU, 0);
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/* enable the instruction cache */
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CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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}
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void Xil_ICacheDisable(void)
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{
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register u32 CtrlReg;
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dsb();
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/* invalidate the instruction cache */
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mtcp(XREG_CP15_INVAL_IC_POU, 0);
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/* disable the instruction cache */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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void Xil_ICacheInvalidate(void)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
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/* invalidate the instruction cache */
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mtcp(XREG_CP15_INVAL_IC_POU, 0);
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_ICacheInvalidateLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
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mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
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{
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u32 LocalAddr = adr;
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const u32 cacheline = 32U;
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u32 end;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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if (len != 0x00000000U)
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{
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/* Back the starting address up to the start of a cache line
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* perform cache operations until adr+len
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*/
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end = LocalAddr + len;
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LocalAddr = LocalAddr & ~(cacheline - 1U);
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/* Select cache L0 I-cache in CSSR */
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
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while (LocalAddr < end)
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{
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/* Invalidate L1 I-cache line */
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asm_inval_ic_line_mva_pou(LocalAddr);
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LocalAddr += cacheline;
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}
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}
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_INVALIDATE)
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Xil_ICacheInvalidateRange((INTPTR)addr, size);
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}
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void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_FLUSH)
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Xil_DCacheFlushRange((intptr_t)addr, size);
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else if (ops == RT_HW_CACHE_INVALIDATE)
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Xil_DCacheInvalidateRange((intptr_t)addr, size);
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}
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rt_base_t rt_hw_cpu_icache_status(void)
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{
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register u32 CtrlReg;
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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return CtrlReg & XREG_CP15_CONTROL_I_BIT;
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}
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rt_base_t rt_hw_cpu_dcache_status(void)
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{
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register u32 CtrlReg;
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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return CtrlReg & XREG_CP15_CONTROL_C_BIT;
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}
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