allows rewrite to interrupt enable/disable api to support independent interrupts management
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libcpu/arm/cortex-m4/README.md
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53
libcpu/arm/cortex-m4/README.md
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## Independent Interrupts Management
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### Introduction
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Calling `rt_hw_interrupt_disable` in multiple places on `rt-thread` may cause interruption delays when the application requires accurate interrupt responses. This is because the system cannot generate any interrupts except abnormal interrupts after disabling interrupts. This is a common problem in the interrupt management of the operating system. The independent interrupt management module is designed to solve this problem.
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The independent interrupt management module is designed to solve the problem of interrupt delays caused by calling `rt_hw_interrupt_disable` in multiple places on `rt-thread`. The module is implemented by rewrite the `rt_hw_interrupt_disable` and `rt_hw_interrupt_enable` functions in the `libcpu` library.
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### Usage
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- Add the following code to the project's `board.c` file.
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```
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#ifdef RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
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#define RT_NVIC_PRO_BITS __NVIC_PRIO_BITS
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rt_base_t rt_hw_interrupt_disable(void)
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{
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rt_base_t level = __get_BASEPRI();
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__set_BASEPRI(RT_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - RT_NVIC_PRO_BITS));
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__ISB();
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__DSB();
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return level;
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}
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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__set_BASEPRI(level);
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}
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#endif /* RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT */
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```
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- Add the following configuration to the `Kconfig` file in the `board` directory.
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```
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menuconfig RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
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bool "Enable independent interrupt management"
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default n
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if RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
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config RT_MAX_SYSCALL_INTERRUPT_PRIORITY
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int "Set max syscall interrupt priority"
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range 0 7
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default 2
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endif
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```
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- Select `RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT` to enable this feature.
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- Select `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` to set the maximum priority of the interrupt that can be called by the system call. The default value is 2.
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### Description
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- The [basepri](https://developer.arm.com/documentation/107706/0100/Exceptions-and-interrupts-overview/Special-registers-for-exception-masking/BASEPRI) register is used in the functions to complete the interrupt management.
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- For example, if `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` is set to 0x01, the system masking only interrupts with a priority of `0x01-0xFF`.
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- Interrupts with a priority of 0 are not managed by the system and can continue to respond to interrupts after `rt_hw_interrupt_disable` is called.
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- When using the [basepri](https://developer.arm.com/documentation/107706/0100/Exceptions-and-interrupts-overview/Special-registers-for-exception-masking/BASEPRI) register for independent interrupt management, note that interrupts with a priority value lower than `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` cannot call any `system API`.
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@ -10,6 +10,7 @@
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-06-23 aozima support lazy stack optimized.
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* 2018-07-24 aozima enhancement hard fault exception handler.
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* 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
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*/
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/**
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@ -32,6 +33,7 @@
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.global rt_hw_interrupt_disable
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.weak rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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MRS r0, PRIMASK
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@ -42,6 +44,7 @@ rt_hw_interrupt_disable:
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.global rt_hw_interrupt_enable
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.weak rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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MSR PRIMASK, r0
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@ -208,6 +211,10 @@ rt_hw_context_switch_to:
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CPSIE F
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CPSIE I
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/* clear the BASEPRI register to disable masking priority */
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MOV r0, #0x00
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MSR BASEPRI, r0
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/* ensure PendSV exception taken place before subsequent operation */
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DSB
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ISB
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@ -11,6 +11,7 @@
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; * 2013-06-18 aozima add restore MSP feature.
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; * 2013-06-23 aozima support lazy stack optimized.
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; * 2018-07-24 aozima enhancement hard fault exception handler.
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; * 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
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; */
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;/**
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@ -36,7 +37,8 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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EXPORT rt_hw_interrupt_disable
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PUBWEAK rt_hw_interrupt_disable
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SECTION .text:CODE:REORDER:NOROOT(2)
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rt_hw_interrupt_disable:
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MRS r0, PRIMASK
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CPSID I
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@ -45,7 +47,8 @@ rt_hw_interrupt_disable:
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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EXPORT rt_hw_interrupt_enable
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PUBWEAK rt_hw_interrupt_enable
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SECTION .text:CODE:REORDER:NOROOT(2)
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rt_hw_interrupt_enable:
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MSR PRIMASK, r0
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BX LR
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@ -208,6 +211,10 @@ rt_hw_context_switch_to:
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CPSIE F
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CPSIE I
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; clear the BASEPRI register to disable masking priority
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MOV r0, #0x00
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MSR BASEPRI, r0
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; ensure PendSV exception taken place before subsequent operation
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DSB
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ISB
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@ -10,6 +10,7 @@
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; * 2013-06-18 aozima add restore MSP feature.
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; * 2013-06-23 aozima support lazy stack optimized.
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; * 2018-07-24 aozima enhancement hard fault exception handler.
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; * 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
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; */
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;/**
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@ -36,7 +37,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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rt_hw_interrupt_disable PROC
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EXPORT rt_hw_interrupt_disable
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EXPORT rt_hw_interrupt_disable [WEAK]
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MRS r0, PRIMASK
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CPSID I
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BX LR
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@ -46,7 +47,7 @@ rt_hw_interrupt_disable PROC
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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rt_hw_interrupt_enable PROC
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EXPORT rt_hw_interrupt_enable
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EXPORT rt_hw_interrupt_enable [WEAK]
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MSR PRIMASK, r0
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BX LR
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ENDP
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@ -208,6 +209,10 @@ rt_hw_context_switch_to PROC
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CPSIE F
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CPSIE I
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; clear the BASEPRI register to disable masking priority
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MOV r0, #0x00
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MSR BASEPRI, r0
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; ensure PendSV exception taken place before subsequent operation
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DSB
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ISB
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