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allows rewrite to interrupt enable/disable api to support independent interrupts management

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jonas
2024-09-30 10:51:44 +08:00
parent 6c4dd1c6ec
commit 47677d9e7f
4 changed files with 76 additions and 4 deletions
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11
libcpu/arm/cortex-m4/context_iar.S
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@ -11,6 +11,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */
;/**
@ -36,7 +37,8 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
PUBWEAK rt_hw_interrupt_disable
SECTION .text:CODE:REORDER:NOROOT(2)
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
@ -45,7 +47,8 @@ rt_hw_interrupt_disable:
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
PUBWEAK rt_hw_interrupt_enable
SECTION .text:CODE:REORDER:NOROOT(2)
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
@ -208,6 +211,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I
; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0
; ensure PendSV exception taken place before subsequent operation
DSB
ISB